| 摘要 |
<p>The present invention relates to a memory cell arrangement. According to this invention, a plurality of memory cells are provided in the region of the main surface of a semi-conductor substrate (10), wherein each memory cell includes at least a MOS-transistor with a source (29), a gate (WL1 or WL2) and a drain (60). The memory cells are arranged in essentially parallel rows, wherein adjacent rows of memory cells are isolated from each other by at least one isolation trench (20) and each include at least one bit-line (60). The bit-lines (60) of two adjacent rows of memory cells are oriented towards each other. According to this invention, the arrangement is designed so that the isolation trench (20) extends deeper into the semi-conductor substrate (10) than the bit-line (60) and so that at least a partial area of the source (29) and/or drain is located under said isolation trench (20). This invention further relates to a method for producing this memory cell arrangement.</p> |
