| 摘要 |
The present invention relates to a computer chip having integrated thereon a CPU, and a cache system being interconnected, and at least one synchronization unit. The chip is setable in one of at least two different running modes, a first one thereof being a DUT mode, and a second one thereof being a MONITOR mode. The MONITOR mode is complementary to the DUT mode. The chip additionally comprises a debug bus connectable to another identical chip for communicating signals enabling the chip and said another chip to run in parallel while said chips being in complementary modes. Said signals comprises synchronization signals generated by said synchronization unit. The present invention further relates to a computer apparatus, and a debugging system both employing at least one such chip. |
