发明名称 DATA PROCESSOR AND DATA ALIGNER
摘要 PROBLEM TO BE SOLVED: To provide a data processor which can perform the same operation regardless of size/align/Endian of data. SOLUTION: In the data processor which has plural bit sizes and processes data, the device is characterized in that it is equipped with an execution unit 101, an access address bus 102 for transferring an access address, an access size signal line 103 for indicating the size of access, a store data bus for transferring store data, a store aligner 105 for converting the store data on the basis of the access address and the size, an internal data bus 106 for transferring the data which the store aligner 105 outputs, an Endian control mechanism 107 for holding the information of Endian in the access address bus, a bus controller 109 for controlling an interface with an external device, an incrementer 110 for performing the increment of the address, an external address bus 111, an external data bus 112, a bite enable signal line 113 and an external device 114.
申请公布号 JP2000003304(A) 申请公布日期 2000.01.07
申请号 JP19980165304 申请日期 1998.06.12
申请人 NEC CORP 发明人 SUGIMOTO HIDEKI
分类号 G06F12/04;G06F5/00;G06F13/36;(IPC1-7):G06F12/04 主分类号 G06F12/04
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