发明名称 DOWN CONVERSION SYSTEM USING A PRE-DECIMATION FILTER
摘要 An HDTV down conversion system including an apparatus for forming a low resolution video signal from an encoded video signal representing a video image. The encoded video signal is a frequency-domain transformed high resolution video signal with motion vectors. The apparatus includes a receiver for receiving the encoded video signal as a plurality of blocks of high resolution frequencydomain video coefficient values. A plurality of blocks comprises a macroblock. A down-conversion filter weights selected ones of the high resolution frequencydomain video coefficient values within each block to generate corresponding blocks of filtered frequency-domain video coefficients. An inverse-transform processor transforms each block of filtered frequency-domain video coefficients into a block of firstfiltered pixel values. A pre-decimation filter performs inter-macroblock inter-block filtering of the plurality of blocks of first-filtered pixel values and provides corresponding blocks of second-filtered pixel values. A decimating processor deletes selected ones of the second-filtered pixel values within each block to provide blocks of low resolution video signal pixel values.
申请公布号 CA2281391(A1) 申请公布日期 2000.04.09
申请号 CA19992281391 申请日期 1999.09.07
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 KIM, HEE-YONG
分类号 H04N7/30;G06T3/40;G06T9/00;H04N7/015;H04N7/26;H04N7/50;(IPC1-7):H04N5/44 主分类号 H04N7/30
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