CIRCUIT FOR GENERATING DATA MEMORY ADDRESS OF LOW POWER PROGRAMMABLE CORE

摘要

PURPOSE: A circuit for generating a data memory address of a low power programmable core is provided to improve an operating speed of a clock by maintaining a cycle per instruction as 1. CONSTITUTION: A circuit for generating a data memory address of a low power programmable core comprises relates to a data memory address generation circuit with an improved speed. The circuit comprises an adder(50), a logic device, an increasing and decreasing device(30), and a selector. The adder receives a sub n-bit command of an address stored in an index register(10) and an address of a command. And the adder outputs a sub n-bit address of a data memory. The logic device receives a carry from the adder and a code bit of the address of the command. The increasing and decreasing device increases and decreases '1' to an upper n-1 bit of the address stored in the register. The selector outputs selectively the address of the upper n-1 bit and the address input to the increasing and decreasing device.