| 摘要 |
PROBLEM TO BE SOLVED: To reduce the load of a phase locked loop PLL circuit included in a data clock generator, to reduce jitters in a generated data clock, and to secure the lock range of the PLL circuit. SOLUTION: The difference between a preceding time stamp SYT value, that has been stored in an SYT reception first-in first-out(FIFO) memory 51 and an SYT value this time is calculated, the difference is shifted to the right by 3 bits to be reduced to 1/8, the preceding time stamp SYT value is stored as it is in a corresponding area SYT 1 of an extended SYT reception FIFO memory 31, an adder 431 sums the preceding time stamp SYT value and the difference/8, the obtained sum is stored in a corresponding area SYT 2 of the extended SYT reception FIFO memory 31, an adder 432 sums the above sum and the difference/8, the sum is stored in a corresponding area SYT 3 of the extended SYT reception FIFO memory 31, and then similarly calculated sums are stored in corresponding areas SYT 4-8 of the extended SYT reception FIFO memory 31. |
