| 摘要 |
PROBLEM TO BE SOLVED: To reduce an entire circuit scale by selecting and outputting a data signal corresponding to a data signal latched by one clock signal, having phase relation which is equal to or more than prescribed the phase difference to the phase of an output clock signal from among plural clock signals. SOLUTION: In n pieces of data signals Do (1.1) to Do (n.n) latched by an output clock signal Co, one data content among them has a possibility of being an indefinite value. For that reason, a selecting and outputting means 40 inputs clock signals Cd (1) to Cd (4), outputted from a synchronous flip-flop 300 and the plural data signals Do (1.1) to Do (n.n), selects one data from among data signals that are not an insufficient value from the plural inputted data signals Do (1.1) to Do (n. n) on the basis of the output signals of the flip-flop 300 and outputs a selected data signal Do' to a synchronous flip-flop 2. |
