摘要 |
<p>PROBLEM TO BE SOLVED: To increase operation processing speed of an one chip microcomputer. SOLUTION: This circuit has arrangement in which addresses of two bytes unit are allotted alternately for flash memories L, R and addresses can be read out with 64 bytes unit. When the last 2 bytes of even numbered or odd numbered large block in the flash memory R are read out, and the beginning 2 bytes of even numbered or odd numbered large block directly after the odd numbered or even numbered block in the flash memory L are read out, an address circuit ADSINC outputs upper 9 bits XADL 9-1 as +1 increment, reverses a FAL7, and supplies it to an address circuit CROSS.</p> |