发明名称 LEVEL CONVERSION CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a level conversion circuit that attains a high conversion rate and low power consumption. SOLUTION: In the level conversion circuit that is provided with an inverter INV that inverts an input signal from an input terminal VIN and outputs the inverted signal, a 1st and transistor(TR) N1 whose gate receives the input signal, a 2nd TR N2 whose gate receives the input signal inverted by the inverter, 3rd and 4th TRs P1, P2 connected between the drains of the 1st and 2nd TRs N1, N2 and a power supply terminal receiving a high voltage power supply, respectively, and where the gates of the 3rd and 4th TRs P1, P2 are in cross connection with the drains of the 1st and 2nd TRs N1, N2, a TR N4 in diode connection is inserted between the connecting point of the output terminal of the inverter INV to the gate of the 2nd TR N2 and the connecting point of the output terminal of the 1st TR N1 to the gate of the 4th TR P2.</p>
申请公布号 JP2000244307(A) 申请公布日期 2000.09.08
申请号 JP19990047063 申请日期 1999.02.24
申请人 NEC CORP 发明人 NAKAMURA HIROISA;JINBO TOSHIKATSU
分类号 G11C16/06;H03K5/02;H03K19/0185;(IPC1-7):H03K19/018 主分类号 G11C16/06
代理机构 代理人
主权项
地址