| 摘要 |
PROBLEM TO BE SOLVED: To provide The method and device for reducing the power consumption of a programmable digital signal processor(DSP) exclusive for a radio telephone or control and improving the execution efficiency of DSP algorithm. SOLUTION: A DSP in a cache consistency circuit has variable instruction length, high code density and easy programming and its structure and a set of instructions are optimized so that DSP algorithm is executed at low power consumption and high efficiency. A cache 814 is formed in a mega-cell mounted on a single integrated circuit 800 to shorten instruction access time. Since the cache 814 is prepared only for writing data, it is unnecessary to measure the consistency of the cache 814. Since a cache consistency circuit 816 is included in the mega-cell and a selected signal is monitored, consistency in the cache 814 in emulation and debugging can be held. |
