| 摘要 |
<p>PROBLEM TO BE SOLVED: To suppress a simultaneous operation of output buffers by correcting a degree of delay of latch sections on the basis of a program process so as to output clocks to the latch sections, to reduce a design period and cost by eliminating the need for any additional circuit. SOLUTION: The simultaneous operation control circuit consists of a parallel layout configuration comprising a plurality of latch sections (flip-flop circuits) 3A-3C connected to output buffers 3AA-3CC, and clocks x, y, z whose delay is differently selected are given to the latch sections 3A-3C by executing a program of a layout tool (CTS function) section 2. Since it is not required to add a delay circuit and a poly-phase clock generating circuit or the like and the simultaneous operation of the output buffers is suppressed through the program processing, occurrence of simple mistakes can be reduced because no manual operation intervenes in the operation and the design man-hours can be decreased. Since no additional circuit is required, the increase in a chip size attended with added number of elements can be suppressed and the cost can be reduced.</p> |
