发明名称 |
Method and apparatus for a single event upset (seu) tolerant clock splitter |
摘要 |
A clock splitter circuit for providing a single event upset (SEU) tolerant clock signal to latches in a space-based environment. The clock splitter circuit can include one or more event offset circuit delay circuits. The event offset delay receives a clock signal and generates a delayed clock signal. The event offset delay circuit can generate an inverted clock signal, a delayed inverted clock signal and a pair of intermediate clock signals. The delayed clock signal and inverted delayed clock signal can be delayed by the known duration of single event effects (SEE). The delayed and undelayed clock signals can be passed to an event blocking filter which can block any disturbance in the delayed and/or undelayed clock signals. A synchronizer can synchronize outputs of the event blocking filter prior to or coincident with being passed to corresponding inverting clock drivers. The synchronizers can also insure that the synchronized blocking filter outputs can not be low simultaneously. Intermediate clocks can also be provided corresponding to the inverting clock drivers. Outputs of the inverting clock driver can be a pair of SEU tolerant non-overlapping clock phase signals for driving one or more latches. |
申请公布号 |
AU4496600(A) |
申请公布日期 |
2000.11.17 |
申请号 |
AU20000044966 |
申请日期 |
2000.04.28 |
申请人 |
LOCKHEED MARTIN CORPORATION |
发明人 |
JOSEPH W. YODER;ABBAS KAZEMZADEH |
分类号 |
G01R31/3185;H03K5/1252;H03K5/151;H03K19/003 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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