发明名称 Processor
摘要 Operator 104 performs a mod2 addition between the MSB of operation data stored in operation data storage section 101 and input data stored in input data storage section 102. Operator 105 performs a mod2 addition between data obtained by shifting the operation data stored in operation data storage section 101 by 1 bit toward the MSB side and coefficients of a generator polynomial stored in generator polynomial storage section 103. Selection section 106 selects either the shift data or the operation result of operator 105 based on the operation result of operator 104 and stores the selected one in operation data storage section 101 as new operation data. This allows the DSP to efficiently process CRC operations with a small hardware investment. <IMAGE>
申请公布号 AU3988100(A) 申请公布日期 2000.11.17
申请号 AU20000039881 申请日期 2000.04.25
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;JUNJI SOMON 发明人 RYUTARO YAMANAKA;TAKASHI TODA
分类号 G06F11/10;G06F7/72;H03M13/00;H03M13/09;H04L1/00 主分类号 G06F11/10
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