| 发明名称 | Array substrate, method for manufacturing the same, and display device | ||
| 摘要 | An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed. The semiconductor layer may be connected to the source electrode and the drain electrode respectively. A first connection region in which a first connection point is located may be arranged between the semiconductor layer and the source electrode. And a second connection region in which a second connection point is located may be arranged between the semiconductor layer and the drain electrode. A length of a shortest distance on the semiconductor layer from the first connection point to the second connection point may be no less than a reference distance which refers to a longest distance of a straight line between any two points among all points on a perimeter of the gate electrode. | ||
| 申请公布号 | US9525075(B2) | 申请公布日期 | 2016.12.20 |
| 申请号 | US201615098398 | 申请日期 | 2016.04.14 |
| 申请人 | BOE TECHNOLOGY GROUP CO., LTD. | 发明人 | Liu Xiang |
| 分类号 | H01L29/10;H01L29/786;H01L29/423;H01L29/66;H01L27/12 | 主分类号 | H01L29/10 |
| 代理机构 | Bakerhostetler LLP | 代理人 | Bakerhostetler LLP |
| 主权项 | 1. An array substrate, comprising: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed, wherein the semiconductor layer is connected to the source electrode and the drain electrode respectively; wherein a first connection region in which a first connection point is located is arranged between the semiconductor layer and the source electrode; wherein a second connection region in which a second connection point is located is arranged between the semiconductor layer and the drain electrode; and wherein a length of a shortest distance on the semiconductor layer from the first connection point to the second connection point is no less than a reference distance which refers to a longest distance of a straight line between any two points among all points on a perimeter of the gate electrode. | ||
| 地址 | CN | ||