HIGH SPEED LEVEL SHIFT CIRCUIT FOR LOW VOLTAGE OUTPUT

摘要

An interface circuit from Common Mode Logic to a low voltage, fixed common mode output, with high current drive. The CML signal is received, and then re-referenced to a low-voltage band-gap supply. The circuit is arranged to provide an output data signal referenced to a second positive reference voltage supply responsive to receipt of a common mode input data signal referenced to a first positive reference voltage supply. The circuit avoids use of vertical PNP transistors in the signal path.