发明名称 EXTENSION EXTENDING SYSTEM IN COMMUNICATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To generate multi-frames with the same phase even without the need for a clock source by allowing a clock generating source to give clock signals with different frequencies to an interface panel and allowing each interface panel to generate M-bit frames with the same phase on the basis of the clock signal whose frequency is a common multiple of the frequencies of a plurality of the extracted clock signals. SOLUTION: A common section 1 generates clock signals whose frequencies are 0.4 kHz and 0.5 kHz and gives thee clock signals to each of interface panels 2 (#1-#4), in which the clock signals are inputted to a common multiple detection circuit 20. Each common multiple detection circuit 20 detects the position of a least common multiple of periods of the two clock pulses so as to find on the least common multiple 0.01 s on the basis of a length T1 of one period of 0.4 kHz (=0.0025 s) and of a length T2 of one period of 0.5 kHz (=0.002 s). Then the common multiple detection circuit 20 generates a clock signal with a period of 0.01 s and gives it to a period generating section 21. Even an existing device can transmit M-bit multi-frame signals with the same phase in this way.
申请公布号 JP2001007805(A) 申请公布日期 2001.01.12
申请号 JP19990172227 申请日期 1999.06.18
申请人 FUJITSU LTD 发明人 YAMADA TSUTOMU
分类号 H04L7/02;H04L12/02;H04M3/00 主分类号 H04L7/02
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