| 摘要 |
PURPOSE: A digital attenuator is provided to improve reliability and reduce manufacturing costs by simplifying a structure of the digital attenuator. CONSTITUTION: A clock generator(10) receives control data(Dc) and outputs the first clock(CK1), the second clock(CK2), and the third clock(CK3). A basic attenuation portion(20) receives input data for attenuation and attenuates the received input data according to the first clock(CK1) and the second clock(CK2). A frequency demultiplier portion(30) is used for latching and demultiplying the output of the basic attenuation portion(20) according to the third clock(CK3). The basic attenuation portion(20) has the first frequency demultiplier(22) and an accumulator(24). The first frequency demultiplier(22) is used for latching and demultiplying input data according to the first clock(CK1). The accumulator(24) is used for adding selectively outputs of the first frequency demultiplier(22) according to the second clock(CK2).
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