发明名称 ADDER CIRCUIT RESET SYSTEM
摘要 PROBLEM TO BE SOLVED: To make continuously cumulatively addable output data by reflecting the added result at the time of reset in the output data without clearing the output data to '0'. SOLUTION: An adder 20 adds input data 33 through an F/F 19 and adds output data 31 through an AND gate 22 and when reset 35 is loaded (reset 35 = '0'), since the output of the AND gate 22 becomes '0', the output of the adder 20 becomes (input data 33) + '0' = (input data 33). Namely, even when reset 35 is loaded, the output data can be continuously cumulatively added by reflecting the added result at the time of reset in the output data without clearing the output data to '0'.
申请公布号 JP2001043066(A) 申请公布日期 2001.02.16
申请号 JP19990214465 申请日期 1999.07.29
申请人 NEC ENG LTD 发明人 HIRAYAMA TATSU
分类号 G06F7/00 主分类号 G06F7/00
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