发明名称
摘要 The image decoder includes a memory which holds two or more previously decoded images. An image processing circuit receives data from the two images. A display receives the images. The processing circuit processes each bidirectional image twice during a display time of an image. The first processing operation is performed while supplying one image directly to the display. The second processing operation is performed while supplying the second image directly to the display. The image is processed by blocks which are regrouped into macroblocks corresponding to squares in the image.
申请公布号 JP3141772(B2) 申请公布日期 2001.03.05
申请号 JP19960084470 申请日期 1996.03.14
申请人 发明人
分类号 G06T9/00;H03M7/36;H04N7/26;H04N7/32;H04N7/46;H04N7/50;(IPC1-7):H04N7/32 主分类号 G06T9/00
代理机构 代理人
主权项
地址