| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce occurrence of malfunction such that mode register set is performed in unintended timing which is caused by a noise superimposed on a clock line and the like in SDRAM control. SOLUTION: This device is provided with a first OR device outputting logical sum of NCS and NRAS, a second OR device outputting logical sum of NCS and NCAS, and a third OR device outputting logical sum of NCS and NWE. And a state in which NCS, NRAS, NCAS, and NWE are all L or an edge of H from L, of L from H is avoided as much as possible.</p> |
