| 摘要 |
PURPOSE: The circuit for controlling a central processing unit is provided to offer a convenience to a user by handling an operating frequency of a central processing unit using software. CONSTITUTION: A central processing unit(130) stores a frequency multiplying(PLL) circuit capable of multiplying an operating frequency therein, and operates and uses a needed operating frequency by the frequency multiplying(PLL) circuit. A south bridge(110) generates A20M#, IGNNE#, INTR, NMI signals which are control information for deciding an operating frequency of the central processing unit(130) when a system is operated normally. A north bridge(140) generates a signal for a reset operation of the central processing unit(130). The north bridge(140) generates a selection signal(CRESET#) for adjusting operation frequency control information of the central processing unit(130) when the reset operation of the central processing unit(130) is performed. A multiplexer(120) switches and outputs the operation frequency control information of the central processing unit(130) in accordance with the selection signal of the north bridge(140). An EEPROM(160) stores a signal generated by adjusting of a dip switch in the prior stage. The EEPROM(160) stores a signal in accordance with the operation frequency control information by a specification of the central processing unit(130). The EEPROM(160) sets a program using an IIC bus mounted in a micro computer(170). A voltage regulator(150) inputs a fixed voltage(3.3 volt) and generates a proper sized voltage for a voltage setting of the central processing unit(130).
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