| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit that can easily shift to a lock state and cope with a sampling frequency over a range wider than a conventional range without extending a clock frequency width more than a conventional lock frequency width. SOLUTION: A higher lock frequency is set in advance when no data stream DF is applied to an input terminal 11, and the lock frequency is shifted to a lower frequency when the data stream DF is applied to the input terminal 11. Thus, locking is easily shifted at the application of the data stream DF. Furthermore, a range counter 38 detects the frequency of the data stream DF, selects any of frequency divider circuits 34-36 and uses the selected frequency divider circuit according to the result of detection. Thus, the PLL circuit can cope with a sampling frequency with a range wider than that of a conventional PLL circuit without extending a variable frequency width of an output of a VCO 21 more than that of the conventional PLL circuit. |
