摘要 |
<p>PROBLEM TO BE SOLVED: To provide a method to attain a high-speed processing of 2N-2N DCT and 2-2N-1-2N DCT or the like under a small circuit scale. SOLUTION: The method adopts a configuration such that 8-8 DCT is conducted by using a MUX 12, a register 141, an adder circuit 181, a subtractor circuit 201, a MUX 241, an adder/subtractor circuit 261, a MUX 281, a register 301, a fixed coefficient multiplier circuit 321, a register 341, a AND circuit 36 and an adder circuit 381 or the like. The 2-4-8 DCT is conducted at part of the circuit conducting the 8-8 DCT by revising or switching the operations of the MUX 12, the MUX 241, the adder/subtractor circuit 261, the MUX 281, the register 301, the fixed coefficient multiplier circuit 321, and the register 341 or the like between the 8-8 DCT and the 2-4-8 DCT.</p> |