发明名称 METHOD AND DEVICE FOR COMPRESSING IMAGE SIGNAL, AND METHOD AND DEVICE FOR EXPANDING THE IMAGE SIGNAL
摘要 <p>PROBLEM TO BE SOLVED: To provide a method to attain a high-speed processing of 2N-2N DCT and 2-2N-1-2N DCT or the like under a small circuit scale. SOLUTION: The method adopts a configuration such that 8-8 DCT is conducted by using a MUX 12, a register 141, an adder circuit 181, a subtractor circuit 201, a MUX 241, an adder/subtractor circuit 261, a MUX 281, a register 301, a fixed coefficient multiplier circuit 321, a register 341, a AND circuit 36 and an adder circuit 381 or the like. The 2-4-8 DCT is conducted at part of the circuit conducting the 8-8 DCT by revising or switching the operations of the MUX 12, the MUX 241, the adder/subtractor circuit 261, the MUX 281, the register 301, the fixed coefficient multiplier circuit 321, and the register 341 or the like between the 8-8 DCT and the 2-4-8 DCT.</p>
申请公布号 JP2001144623(A) 申请公布日期 2001.05.25
申请号 JP19990326188 申请日期 1999.11.16
申请人 NEC CORP 发明人 KATAYAMA YOICHI
分类号 H04N19/60;B24B21/04;B24D11/08;G06F17/14;G06T9/00;H03M7/30;H04N1/41;H04N19/436;H04N19/625;(IPC1-7):H03M7/30;H04N7/30 主分类号 H04N19/60
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