发明名称 TOP GATE FET STRUCTURE AND MANUFACTURING METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide a method of manufacturing a TFT structure through a two-mask process. SOLUTION: A light blocking layer and an interlayer insulating layer are successively laminated on a substrate, a source electrode and a drain electrode are formed thereon (first mask process), a semiconductor layer, a gate insulating layer, and a gate metal layer are laminated successively covering the electrodes, a gate electrode is formed in a second mask process, then the gate insulating layer and the semiconductor layer are etched, and the interlayer insulating film and the light blocking layer are etched using the source and drain electrode as a mask, to obtain a top gate TFT structure. At this point, when each of the interlayer insulating layer and the gate insulating layer is formed of insulating materials, whose main components are SiOX and SiNX respectively and a plasma etching operation is carried out by the use of a mixed gas of CF4 and hydrogen, the gate insulating layer and the semiconductor layer are overetched naturally as against the interlayer insulating layer and the light block layer, so that a TFT structure of high reliability and free of troubles, such as an optical leakage current, can be obtained.
申请公布号 JP2001196589(A) 申请公布日期 2001.07.19
申请号 JP20000000022 申请日期 2000.01.04
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 TSUJIMURA TAKATOSHI;MIYAMOTO TAKASHI
分类号 H01L21/336;G02F1/136;G02F1/1362;G02F1/1368;H01L21/77;H01L21/84;H01L27/12;H01L29/786 主分类号 H01L21/336
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