| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device for facilitating a DC test in addition to an acceleration, a reduction in a power consumption, an acceleration in a speed of a circuit and a decrease in the power consumption, and a method for designing a digital integrated circuit for efficiently designing the digital integrated circuit for facilitating a DC test in addition to an acceleration in the speed of the circuit and a decrease in the power consumption. SOLUTION: The semiconductor integrated circuit device comprises a signal transmission path having a logic gate circuit provided between flip-flops for inputting and holding a signal according to a clock signal. In this case, a signal delay in the path, for example, having an allowance in the signal delay in a relation to a period of the clock signal is constituted of a MOSFET of a first threshold voltage. The signal delay having no allowance in the signal delay is constituted of a MOSFET of a second threshold voltage lower than the first threshold value voltage.</p> |
