| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a delay circuit having a stable delay effect with respect to the change of a signal voltage in the delay circuit using a MOS transistor for load capacity. SOLUTION: The gate of a P-type MOS transistor for load capacity 3 and the gate of an N-type MOS transistor for load capacity 4 are connected to a signal line 10. A register 8 and CMOS inverters 5 and 6 apply a boosted voltage higher than a power voltage to the source/drain of the P-type MOS transistor for load capacity 3. A substrate voltage lower than a ground voltage is applied to the source/drain of the N-type MOS transistor for load capacity 4. Thus, a gate voltage range for giving capacity to MOS transistors for load capacity 3 and 4 is enlarged and stable delay effect is displayed to a signal current flowing in the signal line 10.</p> |
