| 摘要 |
A receiver circuit in a system for transferring data signals among integrated circuits or logic circuit blocks includes a receiving interface for allowing the data signal to be received at a correct timing. The receiving interface includes a detecting circuit for detecting whether or not a signal to be received has arrived at a detecting timing determined on the basis of a clock signal providing a timing base for signal receiving operation, a variable delay circuit inserted in a signal transfer path whose delay factor is controlled in dependence on the result of detection performed by the detecting circuit, and a flip-flop circuit for latching the signal outputted from the variable delay circuit in synchronism with the clock signal.
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