| 摘要 |
PROBLEM TO BE SOLVED: To obtain a wireless receiver that can realize lower power consumption for a demodulation circuit and the entire wireless receiver without placing a limit onto a sampling rate. SOLUTION: The wireless receiver is provided with an RF/IF circuit 1 that receives a signal from a transmitter side and applies analog signal processing to the received signal, an analog/digital converter 2 that converts an analog signal into a digital signal, a demodulation circuit 3 part of or all of which consists of a single digital signal processor or more, that can revise an arithmetic bit length for digital signal processing, and demodulates the digital signal after conversion with the instructed arithmetic bit length, a communication path state estimate section 5 that uses a demodulation result to estimate a state of a communication path, and an arithmetic bit length selection section 6 that instructs the shortest arithmetic bit length satisfying required communication quality based on the estimated communication line state. |
