发明名称 STACKED DIE SET FOR INTEGRATED CIRCUIT PACKAGE
摘要 PROBLEM TO BE SOLVED: To provide a stacked die set for integrated circuit package in which consumption of material and the thickness can be reduced while shortening the production process. SOLUTION: Chips 21a, 21c are attached to the surface of boards 20a, 20b and encapsulated 22 and then chips 21b, 21d are attached to the rear surface of the boards 20a, 20b and encapsulated to produce a stacked die set 2A. The boards 20a, 20b having chips 21a, 21b, 21c and 21d on the surface and rear surface are then stacked and concatenated through protrusions 23a for concatenating carriers electrically thus forming a stacked die set. Since the surface and rear surface of the boards 20a, 20b can be processed simultaneously, production process can be shortened.
申请公布号 JP2002057273(A) 申请公布日期 2002.02.22
申请号 JP20000238145 申请日期 2000.08.07
申请人 ORIENT SEMICONDUCTOR ELECTRONICS LTD 发明人 HSIEN WEN-LO;SO EISEI;NING HUANG;PIN CHEN HUI;SHO KABUN;MING CHANG CHUANG;JO HOSHO;YU HUANG FU;JUI CHANG HSUAN;CHIEH HU CHIA
分类号 H01L25/18;H01L25/065;H01L25/07;H01L25/10;H01L25/11;(IPC1-7):H01L25/065 主分类号 H01L25/18
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