发明名称 Digital clamp for state retention
摘要 Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.
申请公布号 US9484917(B2) 申请公布日期 2016.11.01
申请号 US201213718372 申请日期 2012.12.18
申请人 Intel Corporation 发明人 Raychowdhury Arijit;Augustine Charles;Tschanz James W.;De Vivek K.
分类号 G05F1/10;G05F1/59;H03K19/00;G05F1/46 主分类号 G05F1/10
代理机构 Blakely, Sokoloff, Taylor & Zafman LLP 代理人 Blakely, Sokoloff, Taylor & Zafman LLP
主权项 1. An apparatus comprising: a clamp coupled between a first power supply and a second power supply, wherein the clamp includes a plurality of transistors; a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode, comprising: a comparator to compare the second power supply with a reference, wherein the reference is received at the positive terminal of the comparator and the second power supply is received at the negative terminal of the comparator; anda counter to count up when the second power supply is higher than the reference and to count down when the second power supply is lower than the reference, wherein a higher count of the counter corresponds to more transistors of the clamp being turned off.
地址 Santa Clara CA US