发明名称 |
DRAM CONTROLLER AND CONTROL METHOD |
摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the number of required DRAMs at the time of reading data from the plural DRAMs by an interleave system in real time. SOLUTION: The (n+m) DRAMs and a selection control means for selecting and controlling the DRAM for performing read and the DRAM for performing refresh among the (n+m) DRAMs are provided. For the (n+m) DRAMs, an integer equal to or more than the quotient for which the read time of one DRAM is divided by desired read cycle time by interleave is defined as n and the integer m is determined so as to make the product of the ratio of the time of being in a readable state in a refresh cycle for one DRAM and the number (n+m) of the DRAMs be n or more. The selection and control means successively turns the m DRAMs to a refresh state at a time and turns the remaining n DRAMs to the readable state during the time.</p> |
申请公布号 |
JP2002116953(A) |
申请公布日期 |
2002.04.19 |
申请号 |
JP20000308574 |
申请日期 |
2000.10.10 |
申请人 |
HITACHI ELECTRONICS ENG CO LTD |
发明人 |
OTSUKA YOSHIHIRO |
分类号 |
G06F12/06;G06F12/00;(IPC1-7):G06F12/06 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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