Semiconductor memory circuit

摘要

A semiconductor memory circuit capable of conducting an efficient test by using a memory tester is provided. A semiconductor memory circuit according to the present invention comprises: a memory cell array; a plurality of main data lines for conducting reading and writing every plural bits in parallel; and a shift register for converting parallel data read from said memory cell array to the main data lines into serial data and supplying the converted data to data input/output terminals, and for converting write data supplied from the data input/output terminals in series into parallel data and supplying the converted data to the main data lines, and at least portion of a plurality of the main data lines are arranged so as to be across each other between the memory cell array and the shift register. As a result, data compression is enabled during a test by a memory tester.