| 摘要 |
PURPOSE: A register controlled delay locked loop is provided to perform a high frequency test in a wafer level by using a 90-degree phase shifter for generating an internal clock having a frequency higher than the frequency of an external clock. CONSTITUTION: The first unit register controlled delay locked loop(10) outputs a register value(REG1<n:1>) and generates the first internal clock signal(ICLK1) synchronized with an external clock signal(ECLK). A 90-degree phase shifter(20) shifts the external clock signal(ECLK) as much as a phase difference of 90-degrees. An adder(30) adds the output register value(REG1<n:1>) of the first unit register controlled delay locked loop(10) to an output register value(REG2<n-1:0>) of the 90-degree phase shifter(20). The first unit register controlled delay locked loop(10) is controlled by an output register value(REG3<n-1:0>) of the adder(30) in order to generate the second internal clock signal(ICLK2).
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