| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit which is markedly improved in jitter characteristics (jitter tolerance characteristics, jitter transfer characteristics, and output jitter) required for use in CDR. SOLUTION: A PLL circuit is equipped with a phase comparator 101 which does not depend on the absolute value of a phase difference or a frequency difference between an input signal (NRZ signal) and a PLL output signal but has a binary output (-1, +1), a frequency comparator 102 which has a fixed ternary output (-1, 0, +1), a loop filter 103, and an oscillator (voltage-controlled oscillator or current-controlled oscillator). The PLL circuit is capable of controlling jitter transfer characteristics and jitter tolerance characteristics separately and has a wide pull-in range of frequency without making any adjustments. It is preferable that a charge pump circuit and a Gm cell circuit (V-I converter) are used. |
