| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit that is short in lockup time and does not reflects error signal onto post-stages. SOLUTION: The PLL circuit is provided with a generating means 2 that generates reference signals, variable frequency dividers 4, 8 that apply frequency division to an output signal of a voltage controlled oscillator VCO and output each feedback signal, and a phase comparator 13 that compares the phases of the reference signals with each other and the PLL circuit is configured not to reflect the error signal onto the voltage controlled oscillator VCO. |
