发明名称 |
INTER-PROCESSOR TRANSMISSION DATA ABNORMALITY SIMULATION DEVICE, ERROR VERIFICATION SUPPORT METHOD, RECORDING MEDIUM HAVING ERROR VERIFICATION SUPPORT PROGRAM RECORDED THEREON AND ERROR VERIFICATION SUPPORT PROGRAM |
摘要 |
PROBLEM TO BE SOLVED: To provide an inter-processor transmission data abnormality simulation device for changing data transmitted in inter-processor communication in a multiprocessor device into various pieces of error data and transmitting the resultant data at arbitrary timing, and to provide an error verification support method, a recording medium having an error verification support program recorded thereon and the error verification support program. SOLUTION: The device has a characteristic constitution means provided with: a data trapping means 4 for trapping transmission data 11 transmitted from a first processor 1a; a data change means 5 for performing desired processing on the transmission data 11 trapped by the data trapping means 4 and changing the data into data different from the original data; and a data transmission means 6 for transmitting data changed with the data change means 5 to a second processor 1b as simulated abnormal data 12. |
申请公布号 |
JP2002245020(A) |
申请公布日期 |
2002.08.30 |
申请号 |
JP20010043066 |
申请日期 |
2001.02.20 |
申请人 |
NIPPON TELEGR & TELEPH CORP <NTT> |
发明人 |
SHINOHARA EIJI;HAMADA MAKOTO;YAMAGUCHI TOMOHARU;SUNAGA HIROSHI |
分类号 |
G06F15/177;G06F11/00;G06F11/22 |
主分类号 |
G06F15/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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