| 摘要 |
PURPOSE: A signal level converter is provided, which maintains a high signal fidelity when converting a signal having a PECL(Pseudo Emitter Coupled Logic) level into a signal having a CMOS signal level. CONSTITUTION: The signal level converter comprises a reference voltage bias circuit(11), the first comparator(12), the second comparator(13), the third comparator(14) and a buffer(15). The reference voltage bias circuit generates a reference voltage(VREF). The first comparator compares the reference voltage with an input signal(PECL IN) having a PECL level, and the second comparator compares the reference voltage with the input signal. But the input signal is inputted to a negative input port of the first comparator and to a positive input port of the second comparator. Therefore, the first and the second comparator output signals having increased voltage swing than the input signal and a phase difference of 180 degree each other. The third comparator compares output signals of the first and the second comparator, and outputs a signal having a further increased voltage swing than the input signal. The buffer outputs a signal(CMOS OUT) having a CMOS level by buffering an output signal of the third comparator.
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