| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem of the scan test design needing to comprise at least pins SM, SI and SO but the need exists for reducing the test time, by dividing the scan path to provide the same number of pins SI, SO as the scan path division number, which results in the increased number of test pins. SOLUTION: The integrated circuit has a circuit arrangement comprising scan paths connected to a combined circuit block, each scan path having a plurality of SFFs, and bidirectional pins for inputting a test pattern to the scan path, according to a control signal input mode for applying the test pattern to the combined circuit block and for outputting test results of the combined circuit block in an output mode. For the direction control of the bidirectional pins, an internal circuit is used, which includes chip inputs or counters for control signals from external pins. |
