PROCESSOR, ARITHMETIC UNIT, AND ARITHMETIC METHOD

摘要

PROBLEM TO BE SOLVED: To reduce the number of computing elements constituting a square multiplier for floating-point numbers and also to increase the processing speed by circuit techniques for an arithmetic unit. SOLUTION: The square multiplier for floating-point numbers is provided with a false carry generation circuit 21a which falsely generates information related to carry of prescribed bits in the arithmetic of a variable as an arithmetic object, an MSB(Most Significant Bit) look-ahead circuit 21b which decides the MSB in the arithmetic result in advance from the variable as the arithmetic object, and a combinational circuit which uses information related to carry, which is generated by the false carry generation circuit 21a, to perform arithmetic of the variable while performing rounding processing based on the position of the MSB decided by the MSB look-ahead circuit 21b.