| 摘要 |
A first-in, first-out (FIFO) memory system (10) includes first and second FIFOs (A and B). First and second multiplexers (12, 14) each have two input terminals for receiving data. An output terminal of the first multiplexer (12) is coupled to the first FIFO (A) and an output terminal of the second multiplexer (14) is coupled to the second FIFO (B). In response to the data being one data type, write control logic (90, 95, 100) is used to cause the data to be alternately written to the first and second FIFOs (A, B). In response to the data being a second data type, write control logic (90, 95, 100) is used to cause the data to be simultaneously written to the first and second FIFOs (A, B). |
