AND FAIL DETECTING CIRCUIT, AND SEMICONDUCTOR MEMORY TEST DEVICE

摘要

PROBLEM TO BE SOLVED: To deal with various bit modes while suppressing increase of the circuit scale. SOLUTION: This device has detecting circuits 74, 75 classified by the same number of detection processings, the detecting circuits are provided with fail detecting units 750a, 750b of the same number of detections and an AND circuit 757 outputting an AND fail signal when fail signals are outputted from all fail detecting units, an OR circuit 753 is provided in the fail detecting unit, the OR circuit has a first input terminal 753a corresponding to each allotted logic comparison pin, an inversion mask signal is inputted to the first input terminal corresponding to an arbitrary logic comparison pin excluded from an object of fail detection out of each first input terminal, a fail signal is outputted when a fail signal inputted to the first input terminal in which the inversion mask signal is not inputted.