发明名称 |
VARIABLE DETAIL AUTOMATIC INVOCATION OF TRANSISTOR LEVEL TIMING FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT STATIC TIMING ANALYSIS |
摘要 |
A method and system for designing static timing analysis for application specific-type integrated circuits (ASIC). The method includes use of transistor level timing (TLT) methods that are used only when open channel circuit inputs are detected during the generation of the timing graph.
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申请公布号 |
US2003037306(A1) |
申请公布日期 |
2003.02.20 |
申请号 |
US20010682294 |
申请日期 |
2001.08.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GUTWIN PAUL T.;OSLER PETER J. |
分类号 |
G06F17/50;(IPC1-7):G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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地址 |
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