PROGRAMMING VERIFICATION CONTROL CIRCUIT AND METHOD FOR CONTROL THEREOF

摘要

A programming verification control circuit is disclosed, including: a first decoder circuit for decoding a word line of a memory bit; a first drive circuit for receiving a first voltage and providing the first voltage to the word line of the memory bit based on a decoding result of the first decoder circuit; a second decoder circuit for decoding a control gate of the memory bit; a second drive circuit for receiving a second voltage and providing the second voltage to the control gate of the first memory bit based on a decoding result of the second decoder circuit; and a voltage equalizer for receiving the first voltage, the second voltage and a first enable signal and, in event of the first enable signal being valid, controlling the first voltage and the second voltage to be conducted. A method for controlling the programming verification control circuit is also disclosed.

主权项

1. A programming verification control circuit for controlling a programming verification sequence for a first memory bit of a memory cell, the programming verification control circuit comprising:
a first decoder circuit for decoding a word line of the first memory bit; a first drive circuit for receiving a first voltage and providing the first voltage to the word line of the first memory bit based on a decoding result of the first decoder circuit; a second decoder circuit for decoding a first control gate of the first memory bit; a second drive circuit for receiving a second voltage and providing the second voltage to the first control gate of the first memory bit based on a decoding result of the second decoder circuit; and a voltage equalizer for receiving the first voltage, the second voltage and a first enable signal and, in event of the first enable signal being valid, controlling the first voltage and the second voltage to be conducted, wherein the first decoder circuit comprises a pre-decoder circuit for the word line and a first level shifter, the first level shifter coupled to the pre-decoder circuit for the word line and configured to receive a working voltage of the word line, the first level shifter configured to output a first signal and a second signal equal in magnitude but opposite in sign to the first signal.