| 主权项 |
1. An apparatus comprising:
a memory array; a first logic to detect whether first and second word-lines (WLs) for a row of the memory array are active; and a second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row, wherein the memory array includes memory bit-cells, at least one of which is accessible via at least first and second ports, wherein the first port is associated with the first WL and the second port is associated with the second WL, and wherein the apparatus further comprises: a first switch coupled to first and second bit-lines associated with a memory bit-cell, wherein the first switch is operable to re-route data on the first and second bit-lines to either the first and/or second ports or to the memory array. |
