| 摘要 |
A flash memory constructed of a plurality of memory cells M11, . . . , Mn3 selected by the outputs of an X-decoder 1 and a Y-decoder 2 for generating a row address and a column address is provided with a measurement use write pulse generator circuit 7, which simultaneously supplies write signals of different pulse widths to the memory cells on an identical column, and a select circuit 5, which switches over so as to supply the write signals from the measurement use write pulse generator circuit 7 to the word lines M11, . . . , Mn1 on the identical column during pulse width measurement and supply the word line signal from the X-decoder 1 to the corresponding one word line WL1 during normal access. According to this flash memory, the total write time can be reduced by reducing the frequency of repetition of write and verify.
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