| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To make fine an interlayer via and a wiring pattern for thinning the whole, and to shorten the wiring length in a semiconductor chip for achieving high-speed processing and improving reliability. <P>SOLUTION: With each of unit wiring layers 8-12, two-step first and second exposure treatment having a different amount of exposure in the corresponding site of a via 13 of an insulating layer 24 made of a photosensitive insulating material, and a circuit pattern 25 and development treatment for removing an exposure site, are made. Then, a conductor layer 28 is formed on the entire surface, and at the same time the conductor layer 28 is polished until the insulation layer 24 is exposed for flattening the surface, thus forming the fine and high-density via 13 and the circuit pattern 25 in the insulation layer 24. <P>COPYRIGHT: (C)2003,JPO</p> |
