| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a NAND flash memory device. <P>SOLUTION: First and second input buffer circuits receive N least significant bits (N is any natural number) and N most significant bits respectively out of M bit data inputted through input/output pins. An address register receives an output of the first input buffer circuit as an address responding to address load signals, a command register receives an output of a first address buffer circuit as a command responding to command load signals, and a data input register receives simultaneously output of the first and the second input buffer circuits as data to be programmed responding to the data load signal. The M bit data latched in the data input register is loaded in sense and latch blocks through a data bus. <P>COPYRIGHT: (C)2003,JPO</p> |
