| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a power consumption reduction circuit in which holding of a degree of freedom in the optimization of logic composition due to an HDL and saving of power due to a gating clock can be simultaneously achieved. <P>SOLUTION: The current count value of a current register 3 is sent to a logic 14 for generating a clock enable signal, and the clock enable signal is controlled for the unit of a bit by all current count values. The current count value of the current register 3 on the pre-stage is sent to a logic 15 for passing the clock enable signal on the next stage, and the clock enable signal is controlled for the unit of a bit by the preceding current count value. The clock enable signal to the current register 3 is controlled for the unit of a bit in accordance with a maximum count setting value. <P>COPYRIGHT: (C)2003,JPO</p> |
