Method for detecting a number of consecutive valid data frames and advancing into a lock mode to monitor synchronization patterns within a synchronization window

摘要

One data stream is input to a radio frequency (RF) input terminal of a first receiver interface circuit, and the second bit stream is applied to an RF input terminal of a second receiver interface circuit. Each of the receiver interface circuits includes a Reed-Solomon frame synchronization, forward error correction and derandomizer module receiving the bit stream pattern from the RF terminal of the ground station. Following processing in the derandomizer module, the bit stream is input to a wide band frame synchronization module for synchronization on byte-aligned synchronization pattern at the beginning of each wide-band communications block frame. When synchronization has been established, the data frames are collected for transfer to a memory buffer module. Data buffered in the memory buffer module is direct memory access transferred by a VERSA Module Eurocard (VME) bus interface module to the satellite ground station.