CHIP SCALE PACKAGE WITH SLIT GATE AND FABRICATING METHOD THEREOF

摘要

PURPOSE: A method for fabricating a chip scale package with a slit gate is provided to increase the number of chip arrangements by forming the slit gate whose length is greater than that of a chip, and to prevent the chip from being warped by arranging the slit in parallel with the length direction of a substrate. CONSTITUTION: The slit(205) of the substrate(201) attached to a semiconductor chip(202) adjacent to a main gate of a molding die is made longer than the length of the semiconductor chip. One end of the slit near the main gate extends to the outside of the semiconductor chip. A gate is formed in the semiconductor chip and the substrate. The slit portion is molded by using the gate so that the space necessary for installing an additional gate is reduced to increase the number of chip arrangements.